In this blog entry, I will opine on the application of Harvard Business School’s, Clayton Christensen’s Value Chain Evolution (VCE, http://www.claytonchristensen.com/disruptive_innovation.html) Theory to the semiconductor supply chain. Christensen’s exposition on VCE theory as applied to supply chain management concentrated on micro valuation points in a product’s evolving modular architecture. In this blog entry, I want to focus on macro valuation points in the larger semiconductor supply chain.
During the early days of the inception of the integrated circuit, perhaps only Jack Kilby (Texas Instruments) and Gordon Moore (Intel) could have envisioned the intricate web that has become the semiconductor supply chain. Vertical integration by early adopters is a necessary component to mastering product development and delivery within the supply chain. As with any supply chain in it’s infancy, there are simply too many unknown parameters to modularize the valuation points immediately. During this period of early stage evolution of the semiconductor supply chain, companies were completely vertically integrated for their semiconductor needs. Transistor design, library circuits, functional design and simulation, physical layout, wafer processing, manufacturing test, slicing & dicing, final packaging, more manufacturing tests, product assembly, system test, and shipment were ALL performed by the same company. Not surprisingly, the preeminent company that stood out in those early days, and interestingly enough is the fact that this same company still represents the highest vertical silo within the semiconductor industry, of vertical integration of their semiconductor supply chain was the IBM Corporation.
Three semiconductor supply chain modularities, a fourth is emerging
As outlined in the figure above, the semiconductor industry has undergone three (3) major inflections in it’s value chain: (1) the Electronic Design Automation (EDA) software tools used to design integrated circuits, (2) multi-tenant manufacturing silicon foundries that gave rise to the fabless semiconductor company, and (3) a Semiconductor Intellectual Property (SIP) market that drives ultra-large scale integration for Systems-on-Chip (SoC) development. Stimulated by the advance of the Internet, a utility computing service model, aka, cloud computing, we are now seeing a fourth valuation point inflection emerge in the form of outsourcing of the semiconductor design-to-release-manufacturing workflow infrastructure. This fourth inflection point is a manifestation of the first WorkFlow-as-a-Service (WFaaS) cloud design pattern.
My primary contribution in this blog entry is establishing a direct correlation for each of the four (4) semiconductor supply chain inflection points with a distinct identity profile: (1) EDA Supplier, (2) Foundry, (3) IP Provider, and (4) Designer. The taxonomy of such identity profiles will define and intersect issues of privacy, security, anonymity, certification, authentication, governance, accountability, and reputation within a cloud computing enterprise architecture. When implementing a cloud-based WorkFlow-as-a-Service (WFaaS) for semiconductor design-to-release-manufacturing, the four (4) semiconductor supply chain identity profiles exist as part of a reputation system. Multiple identity profiles may be assigned to users, but must still adhere to identity profile restrictions. When class objects are augmented with cross-cutting concerns, such inter-class characteristics are called aspects. The application of aspect-oriented programming to XML schemas used in WFaaS cloud services may prove to be an optimal solution. This is another area of active research for a future blog entry.
(1) Emergence of the EDA software industry (EDA Supplier Class)
Moore’s Law is at the root of integrated circuit complexity. The “march to the sea” campaign for ever increasing transistor density and performance created what has become total dependence on computer-aided design software applications for the successful design and manufacture of all semiconductor components. Computer-aided design software for semiconductors, aka, Electronic Design Automation (EDA) was birthed and matured in corporate research laboratories and leading academic engineering institutions. Early EDA software applications (“tools” to design engineers), were not developed by professional software engineers, but by the engineers who actually used the software. If there was a bug in the EDA software, it was identified by the user and in early cases, fixed in the source code by the user.
As the EDA tools were required to do more and more, the application’s complexity increased. Over time the engineering team’s dependency upon the EDA tools became intractable, and engineering management was forced to form separate EDA design teams within their engineering organizations. As the engineering organizations continued to expand, the EDA tool usage disseminated across corporate business units, with correspondingly increased demands upon EDA teams to train and support their design engineering customer base. The immaturity and lack of standards created a wide range of engineering productivity, component performance, and final product differentiation for semiconductor companies. Maintaining an edge in EDA tool capability translated directly into market advantages. Semiconductor companies protected their EDA tool capabilities with as much security as their semiconductor intellectual property.
As semiconductor companies grew and semiconductor design teams and employees migrated between companies, the EDA technology osmosis eroded the competitive advantages in EDA tools. What shortly followed was the formation of startup companies armed with the copyright and licensing for the EDA software applications formerly held by their new customers. Today, the big three (3) EDA companies, Synopsys, Cadence Design Systems, and Mentor Graphics, dominate the approximately ~$3.5B/yr EDA software market.
(2) The Fabless Semiconductor Industry (Foundry Class)
Wafer cooking!
The “big daddy” of the semiconductor supply chain is the silicon foundry. If you’re thinking of building your own 32nm silicon wafer processing facility, you better have north of $4B in your bank account. Silicon foundry processing is a “pay to play” game and not for the faint of heart. The expression “Real men own fabs”, was not intended as a sexist remark, but became a true symbol of power in the semiconductor industry. Just ask the largest multi-tenant silicon manufacturing company in the world, Taiwan Semiconductor Manufacturing Corporation (TSMC), how it feels to own their own silicon foundry.
The enormous fixed cost capital that came into play for manufacturing and maintaining a leading edge silicon foundry has been the sole driving force behind the modularity of this inflection point in the semiconductor supply chain. Why the sole driving component? Because there can be tremendous differentiation that can be gained in multiple product dimensions from an advanced silicon foundry process. The most recent example is the business case for the advanced silicon process technology, Silicon-On-Insulator (SOI, pronounced soy) advanced primarily by the IBM Corporation. SOI processing had distinct technological advances in both power and performance, but the necessary silicon wafer manufacturing volumes that were needed to make the investment in SOI fabs profitable was higher than IBM’s internal consumption. Unless IBM sought to service external customer SOI wafer demand, while also partnering with other silicon foundries, even with IBM’s vast capital resources, the cost of capital investment for maintaining a proprietary advantage of the SOI technology could not be justified.
The SOI case analysis reflects the most recent activities in silicon fab partnership. Let’s go back and re-examine the emergence of the dedicated silicon fabs that gave rise to the fabless semiconductor company. The following silicon foundry companies were business “carve-outs/spinoffs” from larger technology congomerates: (1) Infineon (Siemens), (2) Qimonda (Infineon), (3) Agilent (HP), (4) NXP (Philips), (5) Freescale (Motorola), (6) HiSilicon (Huawei, actually fabless, but noteworthy as a separation of semiconductor component design from the systems business of Huawei), (7) ST-Micro (Thompson), (8) GLOBALFOUNDRIES (AMD) (unique in that a pure play semiconductor component company also found the need to spin off the foundry part of the business). This is not an exhaustive list, compiled right off the top of my head. But take a look at this dominant market trend. None of the technology companies listed in parentheses were able to justify a model where they were able to maintain a profitable core business unless they jettisoned their respective company’s silicon fabrication facilities. While the IBM Corporation did not spin off its silicon fabs, IBM did form the Microeletronics Business Unit. IBM Microelectronics does have a fabless business model. Although, I don’t have specific numbers, my present understanding is that greater than 50% of IBM Microelectronics revenues comes from external customers.
What became clear to all of these semiconductor companies was that the silicon wafer processing valuation point in the semiconductor supply chain was able to achieve so much differentiation, that the resources needed to maintain a competitive advantage could not be profitably integrated into their adjacent core business models. The cost of capital needed to invest in the fixed costs for silicon foundry operations required a completely different business model, i.e. an amortization of those fixed costs across many customers, a multi-tenant manufacturing facility. Imagine how other forms of heavy manufacturing implore multi-tenancy in their manufacturing operations. Some companies just manufacture one modular component that is supplied to multiple customers. The example that comes to mind here is Cummins Diesel. Cummins manufactures diesel engines that are used in multiple company’s final assembled industrial and commercial trucks. Other component suppliers manufacture a catalog of modular assemblies that are sold and distributed to many different systems integrators. The case of a multi-tenant silicon foundry manufacturing operation is fundamentally different.
In the case of a silicon foundry, the outsourced modularity lies strictly in the process of manufacturing transistors and interconnecting those transistors on a silicon wafer, NOT in the final component’s functionality. In the previous heavy manufacturing example, it is the modular component’s functionality that has the outsourced value, NOT the process of manufacturing the component. It is important that the reader detect and understand the difference that is cited here. Why? Because it is in this subtle, yet vitally important, difference that forces upon Foundry class stakeholders a heterodox dependency for success upon two of the other three much less capital intensive stakeholders, namely, IP Providers and EDA Suppliers.
The key to a silicon foundry’s profitability is maintaining a full capacity of silicon wafers to process. As to how that manufacturing capacity is filled is left up to a foundry’s sales and marketing teams. The first order of foundry competitiveness is having a silicon process that has the desired transistor performance and transistor density. Due to the high fixed costs, consolidation and exits from the foundry market have reduced the number of pure play silicon foundries. In order to stay in business, every foundry will deliver similar process offerings to their customers. In no small part due to silicon foundry alliances between multiple foundry companies, the process offerings may be virtually identical as the alliance members will share process intellectual property. The second order of differentiation for a foundry to a Designer class customer then becomes the foundry’s catalog of FUNCTIONAL semiconductor IP (IP Provider) AND the foundry’s DESIGN REFERENCE FLOW (EDA Supplier).
More to come…
(3) Systems-on-Chip (SoC), an evolution in ultra-large scale integration (IP Provider Class)
Systems-on-Chip
Even from the earliest days of my career as a design engineer, I’ve always been a keen observer in design methodology processes associated with integrated circuit design. Every chip designer had this dream of starting with a clean slate of silicon, designing every logic gate and circuit on the chip. Ah, how quickly the dreams of youth are shattered! The financial reality of chip design is quickly seared into the mindset of engineering management…these devices are VERY hard to design, and even harder to get right on the first pass of manufacturing, and oh yes, chips are very expensive to manufacture! By the way, don’t forget that for every product defect that is a result of a malfunctioning integrated circuit component, six (6) to nine (9) months of market “opportunity cost” (oh no!!! not the “opportunity cost” factor!) is lost while the semiconductor component is fixed and undergoing another manufacturing spin.
In today’s fast moving product cycles, a manufacturing re-spin of a chip component targeted for product shipment most likely means that the chip and it”s associated design team will have to find another component to work on. The reality that set in quickly was that success in chip design and manufacturing was INVERSELY correlated to the amount of INCREMENTAL new functionality that had to be designed into the component. The more functional design modules of a working chip design that could be re-used in the new chip, the quicker time to market and higher level of confidence in achieving a first pass design. This was the foundation upon which the Semiconductor Intellectual Property (SIP) market was built upon.
The problem with the early days of SIP re-use lay in the lack of on-chip modular interfaces. Another classic example of Value Chain Evolution(VCE) Theory that was applied to the semiconductor supply chain. As a system becomes more complex, modularity increases. Early chip design architectures had crude levels of modularity and hierarchy. Entire chip design methodologies evolved around modular architectures. The lack of modularity in early chip design created EXTREMELY hard re–use scenarios that were fraught with as much uncertainty as if the design had been started from scratch. In fact, what many engineering management teams did not understand in the early days of chip architecture was that free-for-all design modularity schemes and methods by various design engineering teams created nightmarish episodes of attempts by design teams to re-use functionally correct modules in a new chip architecture. Unless they had lived previous engineering lives integrated circuit design engineers, it was a conundrum to many engineering managers as to why they were still running into the same issues with chip designs that had high percentages of re-used modules, but the design cycle was taking practically the same amount of time. All of these problems centered around the lack of modular interfaces in evolving chip architectures.
The emergence of Register Transfer Languages (RTL), such as Verilog and VHDL, made great strides in standardizing modular interfaces for chip designers. Subsequent modularity evolutions that quickly materialized gave rise to the concept of a System-on-Chip (SoC). The SoC design mentality changed the approach chip architects used in modularity and hierarchy. Chips were now being designed with re-use and incremental re-spins in mind. The silicon upon which the circuits were being laid was merely a canvas for the final picture of design. Take a look at any modern day integrated circuit layout through the lens of a microscope and a layman can quickly identify key components of modularity.
I also do not want to discount the importance of the effect of Moore’s law with respect to the drive toward SoC modularity. The enormous growth in transistor density, that is now at 32nm, has provided such a large canvas of silicon upon which functional capability can be manufactured, it has become extremely difficult to maintain ALL of the needed expertise in house to design and maintain all of the functional modules. Functionality that was previously contained in integrated circuit components from other semiconductor manufacturers and purchased for final product assembly on a printed circuit board with other integrated circuits, was now being integrated on the SAME integrated circuit. Semiconductor component companies didn’t really have an option to choose to not move toward SoC scales of integration. Silicon foundries could not afford to maintain older silicon processes with less transistor densities, forcing component designers into lower transistor geometries. In order to maintain competitiveness with other component manufacturers, the more functionality that could now be integrated, the more attractive a company’s component would be to systems integrators.
If became clear that VCE Theory would quickly kick into play for SoC component design. By modularizing the functional component interfaces, a SIP market could now emerge to play a role in providing known, good, tested, high quality SIP to potential component design teams. How would the SIP provider recoup their investment in the design and test of the SIP products? Through royalty licensing models extracted at the point of manufacture! I want the reader to remember this key business model concept, namely, the extraction of VALUE AT THE POINT OF MANUFACTURE!! The change in the valuation point of a supply chain, where that which is good enough will be outsourced, is exemplified in no greater fashion than in the case of the emergence of the SIP market and the extraction of compensation through manufacturing volumes!
IP-XACT – XML Schema for SIP Re-use
The red-headed step child of the semiconductor industry? Not hardly! More…
(4) Silicon Stratus – cloud-based semiconductor design-to-release-manufacturing (Designer Class)
Modern day 32nm Chip Designer
The three (3) previous inflection points in the semiconductor supply chain define unique identity profiles. The fourth inflection point finalizes the picture of the semiconductor supply chain by focusing upon the Designer class of the development cycle. Clearly, not a minor player or role, the Designer class is at the center of the semiconductor supply chain. The Designer class identity profile within the semiconductor supply chain is at the nexus of the three (3) identity profiles. The Designer class is the seed that conceives the rest of the semiconductor supply chain. The other three classes exist BECAUSE of the Designer class. They are the liberating point that gave rise to the emergence of the other three identity profiles of the semiconductor supply chain. I know that is may sound to overtly parochial, but I do mean to impart the importance of this relationship. We’ve got to recognize when and where the “tail is wagging the dog” in the semiconductor market.
Designers are the primary consumers in the semiconductor supply chain. Think of it as a transformation from the first Ironman suit that Robert Downey Jr. created in the caves of Afghanistan to the final version he cooked up in his basement in Malibu! The Designer class today has stripped themselves of all distractions, leaving only the lean meat of functional design creativity in their domain…ALMOST!! While the Designers have “cleaned up” their design responsibilities, as the centrum of the supply chain, they have created a “head of line blocking”, logistical nightmare that has forced the Designer class into a new management role for each of the three (3) identity profiles’ informational exchange. The informational exchange between Foundries, EDA Suppliers, and IP Providers has become too reliant upon the Designer class to drive their own internal processes. As a result, the Designer must manage the actual semiconductor design-to-release-manufacturing methodology process needed to actually design semiconductor components.
The Designer class has outsourced that which is “good enough” (Foundry, EDA Supplier, and IP Provider) and retained and preserved those key core skills that define who they truly are within the semiconductor supply chain. Now that the Designer class has disintegrated their supply chain into it’s fundamental components, the final step in attaining the Xanadu of productivity is to RE-INTEGRATE the four (4) supply chain identity profiles into a secure, multi-tenant, collaboration IT environment. This is where the potential of the Internet begins to reach a state of Nirvana for Designers through the realization of a utility computing or cloud computing model for a semiconductor design-to-release-manufacturing WorkFlow-as-a-Service (WFaaS), i.e. a Silicon Stratus!
VCE Theory produces another child in the semiconductor supply chain…the Silicon Stratus!
More to come…
J. Marc Edwards' techno-blog 